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BE-BI-PM Section


HIE-ISOLDE diagnostic boxes

Fig. 1: Picture of a short diagnostic box Fig. 2: Rendering of the inside of a diagnostic box. The Faraday cup, the scanning slit and the collimating blade are clearly visible

Documents

Control and infrastructure

Gain and Gate meaning

FPGA
name
FPGA
pin
VME
pin
Schematics
label
DB25
pin
Function Logic
AmpliGain_0_r4[3] AB18 p2-A3-sc0 Cmd/1000prea-sc1 7 Input stage gain HIGH/Open \(V_{out}= 4.98 \cdot 10^6 I_{in}\)
LOW/Closed \(V_{out}= 49.8 \cdot 10^6 I_{in}\)
AmpliGain_0_r4[1] AA18 p2-A2-sc0 Cmd/100x-sc1 8 Integrator gain HIGH/Open \( dV_{out}/dt= 10.15 \cdot 10^3 V_{in} \)
LOW/Closed \(dV_{out}/dt= 1.015 \cdot 10^6 V_{in}\)
AmpliGain_0_r4[2] AB20 p2-C1-sc0 Cmd/100prea-sc1 11 Automatic offset
correction
HIGH/Open Correction ON
LOW/Closed Correction OFF
AmpliGain_1_r4[1] AB17 p2-A5-sc1 +4
-17
Integrator gate HIGH/Open Integrate
LOW/Closed Discharge
  • AmpliGain_X_r4[index] index starts at 0
  • The preamplifier Input impedance is 100 kOhm
  • The maximum preamplifier output is +7 V
  • The ADC range is +/- 10V and it has 12 bits
  • AmpliGain_0_r4[0] is don't care

Preamplifier gains

\(V_{out}= g_{amp} \cdot g_{int} \int I_{in} dt = G \int I_{in} dt\)

Gain AmpliGain_0_r4
[1]
AmpliGain_0_r4
[2]
AmpliGain_0_r4
[3]
AmpliGain_0_r4
Reg
Vo/Qin
[V/pC]
Qin/Vo
[pC/V]
Max current
@ 10Hz [pAe]
LSB
@ 10Hz [fAe]
x 1 1 1 1 0x0E \(0.05055\) \(19.8\) 1386 967
x 10 1 1 0 0x06 \(0.5055\) \(1.98\) 138.6 96.7
x 100 0 1 1 0x0C \(5.055\) \(0.198\) 13.86 9.67
x 1000 0 1 0 0x04 \(50.55\) \(0.0198\) 1.386 0.967

Timing setup

For the acuisition of the FC current the acquisition timings have to be setup as following:

  • The clock of the ADC should be set after the beam but before the end of the gate
  • The gate should start just before the beam and end after the ADC has acquired the data
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Page last modified on April 04, 2017, at 06:51 PM EST